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march 2010 doc id 17269 rev 1 1/38 1 l9958 low r dson spi controlled h-bridge features programmable current regulation peak threshold by spi up to 8.6 a typ. operating battery supply voltage 4.0 v to 28 v operating v dd supply voltage 4.5 v to 5.5 v all pins withstand 19 v, vs and output pins withstand 40 v full path r on from 100 m (at t j = -40 c) to 300 m (at t j =150 c) logic inputs ttl/cmos-compatible operating frequency up to 20 khz 16-bit spi interface for configuration/diagnostics, daisy chain capability over temperature and short circuit protection v s undervoltage disable function v dd undervoltage and overvoltage protection v dd overvoltage detection open-load detection in on condition full diagnostics in off state enable and disable input low stand by current (<10 a) voltage and current slew-rate control for low emi, programmable through spi available in three power packages description the l9958 is an spi controlled h-bridge, designed for the control of dc and stepper motors in safety critical applications and under extreme environmental conditions. the h-bridge is protected against over temperature, short circuits and has an undervoltage lockout for all the supply voltages v s and v dd , and for overvoltage on v dd . all malfunctions cause the output stages to go tristate. detailed failure diagnostics on each channel is provided via spi: short circuit to battery, short circuit to ground, short circuit overload, over temperature. open-load can be detected in on condition, for the widest application ranges. current regulation threshold can be set by spi from 2.5 a to 8.6 a (typ.), in 4 steps. guaranteed accuracy is 10 % on all temp range, using an external reference resistor with 1% accuracy over all temp range. current limitation threshol d is linearly reduced by temperature over 165 c.and a thermal warning bit is set by spi. the h-bridge contains integrated free-wheel diodes. in case of free-wheeling condition, the low side tran sistor is switched on in parallel of its diode to reduce power dissipation. a multiple wire bonding technique, as well as st proprietary package design is making l9958 compatible with three power packages, for maximum flexibility: powerso-20 package (medium power, jedec standard mo166); powerso16 package (medium power, lower cost); powersso24 package (low power, very low cost jedec standard mo271a). table 1. device summary order code package packing l9958 powerso-20 tube L9958SB powerso16 tube l9958xp powersso24 tube powerso-20 powersso24 powerso16 www.st.com
contents l9958 2/38 doc id 17269 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 powerso-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 powerso16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 powersso24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.1 di and en inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.2 dir and pwm inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3.1 daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 spi communication failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 5 v and 3.3 v output compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 temperature-dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 current regulation with low-inductive loads . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 slew rate control in case of current limi tation on low-side . . . . . . . . . . . . 17 5 diagnostics and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 reset requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.2 diagnosis reset bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 protection and on state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.1 over-current on high-side - short to ground . . . . . . . . . . . . . . . . . . . . . . 20 5.2.2 over-current on low-side - short to vs . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 short circuit over-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.4 open load in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.5 over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
l9958 contents doc id 17269 rev 1 3/38 5.2.6 vs under-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.7 vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.8 vdd under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.9 output short protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 off-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.2 open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 h-bridge functional status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.1 device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.2 device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.4.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.4 digital inputs: ttl // 3.3v / 5v cmos compatible . . . . . . . . . . . . . . . . . 29 6.4.5 bridge output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.6 over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4.7 current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . 30 6.4.8 diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4.9 off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4.10 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of tables l9958 4/38 doc id 17269 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. powerso-20 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. powerso16 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. powersso24 pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. control pins en, di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. control pins dir, pwm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. configuration protocol (cfg_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. diagnosis protocol (dia_reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. current limitation programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. slew rate control on low side mos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. vs under-voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20. spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 21. digital inputs: ttl // 3.3v / 5v cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. bridge output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 23. over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 24. current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 25. diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 26. off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
l9958 list of figures doc id 17269 rev 1 5/38 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. powerso-20 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. powerso16 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. powersso24 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. h-bridge configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. spi protocol structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. fsi bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. daisy chain topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. spi zero clock communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 11. current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. temperature dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. current regulation with different loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. slew rate switching strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15. diagnostics for scb / scol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. open load in on state - low-side current recirculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 19. open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. off-state diagnostic principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. thermal impedance (junction-ambient) of power packages . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22. application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. powerso-20 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 24. powerso16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 25. powersso24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 36
block diagram l9958 6/38 doc id 17269 rev 1 1 block diagram figure 1. block diagram out 1 out 2 vs gnd gate driver charge pump vs undervoltage vdd under-overvoltage control logic spi reference current generator so si cs sck vddio en di pwm dir vdd rext overtemperature current limitation current monitor cp diagnostic over-current detection over-current detection to control logic block to control logic block to control logic block ac00654
l9958 pins description doc id 17269 rev 1 7/38 2 pins description 2.1 powerso-20 the exposed slug must be soldered on the pcb and connected to gnd. figure 2. powerso-20 pin connection (top view) table 2. powerso-20 pin function pin n name description 1 gnd ground 2 so serial out 3 vddio supply voltage for spi 4 cs chip select 5 cp charge pump 6 vs supply voltage 7 dir direction input 8out1output 1 9 di disable 10 gnd ground 11 gnd ground 12 en enable 13 out2 output 2 14 pwm pwm input 15 rext external reference resistor 16 si serial in 17 sck spi clock 18 vdd supply voltage 19 n.c. not connected (to be connected to gnd on the pcb) 20 gnd ground gnd di en vddio cs vs cp dir out1 so gnd 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 gnd out2 pwm si rext sck vdd n.c. gnd ac00655
pins description l9958 8/38 doc id 17269 rev 1 2.2 powerso16 the exposed slug must be soldered on the pcb and connected to gnd figure 3. powerso16 pin connection (top view) table 3. powerso16 pin function pin no name description 1 gnd ground 2 so serial out 3cschip select 4 cp charge pump 5 dir direction input 6 out1 output 1 7didisable 8 pgnd power ground 9enenable 10 out2 output 2 11 pwm pwm input 12 rext external reference resistor 13 vs supply voltage 14 si serial in 15 sck spi clock 16 vdd supply voltage ac00656 gnd cs cp out1 dir di pgnd so 8 7 6 5 4 3 2 9 10 11 12 13 15 14 16 1 en out2 rext pwm vs si sck vdd
l9958 pins description doc id 17269 rev 1 9/38 2.3 powersso24 although this package has two separate pins for the ground (pin11 = pgnd = power ground and pin22 = gnd = logic ground), the device is designed to work with shortening ground and is mandatory that the two pins have to be connected nearby the ic on the pcb. the exposed slug must be soldered on the pcb and connected to gnd. figure 4. powersso24 pin connection (top view) table 4. powersso24 pin function pin no name description 1, 2, 12, 13, 14, 23, 24 n.c. not connected 3 so serial out 4 vddio supply voltage for spi 5 cs chip select 6 cp supply voltage for spi 7 vs supply voltage 8 dir direction input 9 out1 output 1 10 di disable 11 pgnd power ground 15 en enable 16 out2 output 2 17 pwm pwm input 18 rext external reference resistor 19 si serial in 20 sck spi clock 21 vdd supply voltage 22 gnd ground n.c. out1 out2 so vddio cp cs vs dir n.c. di 10 8 9 7 6 5 4 3 2 17 18 19 20 21 23 22 24 16 1 15 en pgnd nc n.c. 12 11 14 13 nc pwm rext sck si vdd gnd n.c. n.c. ac00657
device description l9958 10/38 doc id 17269 rev 1 3 device description 3.1 supply range the l9958 has an operating supply range from "vs_uv" (battery monitoring) up to 28 v. however, the device is tested until 16 v; the functionality of the device is guaranteed until 28 v. the absolute maximum rating is defined to 40 v dc. 3.2 control inputs the bridge is controlled by the inputs pwm, dir, en and di. all the digital inputs and outputs of the l9958 are compatible with 3.3 v and 5 v cmos. the power stages output out1 and out2 are controlled by the direct inputs dir and pwm as given in ta b l e 5 . the dir input gives the direction of output current, while the pwm input controls whether the current is increased or reduced. 3.2.1 di and en inputs the pin di is internally pulled-up and high active. when di is active (set to high), the bridge is set to tristate, whatever the state of the dir and pwm inputs. all the data stored in spi registers are not reset and spi communication with the mcu is still possible. when di is inactive (set to low), the bridge is controlled by the dir and pwm inputs. the pin en is internally pulled down and high ac tive. when en is inactive (set to low), the bridge is set to tri-state, whatever the state of the dir and pwm inputs. all the data stored in spi registers are not reset and spi communication with the mc u is still possible. when en is active (set to high), the bridge is controlled by the dir and pwm inputs. the coding is performed as shown in the next table. the state of the bridge is transferred in the diagnostic register in a bit called "act". table 5. control pins en, di en di bit ?act? bridge status 0 0 0 tri-state 0 1 0 tri-state 1 0 1 on-state 1 1 0 tri-state
l9958 device description doc id 17269 rev 1 11/38 3.2.2 dir and pwm inputs the pins dir and pwm are internally pulled down. the bridge is controlled by these two inputs according to the table below. figure 5. h-bridge configurations the outputs can be disabled (set to tri-state) by the disable and enable inputs di and en. input di has an internal pull-up. input en ha s an internal pull-down . during freewheeling phase, an active freewheeling on the low-side mos is automatically set, switching on the power transistor in parallel to the internal freewheeling diode. table 6. control pins dir, pwm dir pwm out1 out2 bridge status hhhlforward l l l l freewheeling low lhlhreverse h l l l freewheeling low out1 out2 i l dir=1, pwm=1 (forward) out1 out2 i l dir=0, pwm=1 (reverse) v v out1 out2 i l dir=1, pwm=0 (freewheeling ls) out1 out2 i l dir=0, pwm=0 (freewheeling ls) v v ac0065 8
device description l9958 12/38 doc id 17269 rev 1 3.3 serial peripheral interface (spi) the spi is used for bidirectional communication with a control unit, allowing ic configuration, diagnosis and identification. l9958 can also be used in daisy-chain configuration (number of device in the daisy chain is not limited). the spi interface of l9958 is a slave spi interface: the master is the c which provides cs and sck to l9958. transfer format uses 16 bits word in case of single device configuration and multiple of 16 bits word in case of daisy chain configuration. the first answer after power-on-reset is the ic identifier. a command sent by the c during transfer n is answered during transfer n+1. so is clocked on sck rising edge. si is sampled on falling edge. when cs = '1' and during power-on reset, so is in tri-state. otherwise, the spi interface is always active. settings made by the spi control word become active at the end of the spi transmission and remain valid until a different control word is transmitted or a power on reset occurs. at each spi transmission, the diagnosis bits as currently valid in the error logic are transmitted. details on diagnosis are described in section 5 . figure 6. spi protocol structure between cs falling edge and sck rising edge, an internal signal called "fsi bit" is set asynchronously on so output. this can be useful to have internal information on the device without stimulating the sck clock. the definition of the fsi bit is presented in the diagnostics chapter. figure 7. fsi bit except the enable / disable bit (?act? pin), all the bits of diagnosis register are latched and can be released by: diagnosis register read by spi power-on-reset condition. the coding for the configuration and diagnosis registers is reported in the table below. cs command n answer to cmd n-1 answer to cmd n command n+1 si so ac0068 0 cs sck fsi bit so ac00681 lsb 12 msb . . . . . .
l9958 device description doc id 17269 rev 1 13/38 table 7. configuration protocol (cfg_reg) bit name description config. value after reset 0 - lsb res reserved ? 1 dr diagnostic reset bit 0 2 cl_1 bit1 for regulation current level 0 3 cl_2 bit2 for regulation current level 1 4 res reserved ? 5 res reserved ? 6 res reserved ? 7 res reserved ? 8 vsr voltage slew rate control value 0 9 isr current slew rate control value 0 10 isr_dis current slew rate control disable 0 11 ol_on open load in on state enable 0 12 res reserved ? 13 res reserved ? 14 0 ?0? to be written ? 15-msb 0 ?0? to be written ? table 8. diagnosis protocol (dia_reg) bit name description status after reset bit state dr impact h-bridge status 0-lsb ol_off open load in off condition 0 latched ? ? 1 ol_on open load in on condition 0 latched ? ? 2 vs_uv vs undervoltage 0 not latched ? hi-z if ?1? 3 vdd_ov vdd overvoltage 0 latched x hi-z if ?1? 4 ilim current limitation reached 0 latched ? ? 5 twarn temperature warning 0 latched ? ? 6 tsd over-temperature shutdown 0 latched x hi-z if ?1? 7 act bridge enable 1 not latched ? hi-z if ?0? 8 oc_ls1 over-current on low side 1 0 latched x hi-z if ?1? 9 oc_ls2 over-current on low side 2 0 latched x hi-z if ?1? 10 oc_hs1 over-current on high side 1 0 latched x hi-z if ?1? 11 oc_hs2 over-current on high side 2 0 latched x hi-z if ?1? 12 null not used ? ? ? ? 13 null not used ? ? ? ? 14 sgnd_off short to gnd in off condition 0 latched ? ? 15-msb sbat_off short to battery in off condition 0 latched ? ?
device description l9958 14/38 doc id 17269 rev 1 3.3.1 daisy chain operation several l9958 can be connected to one spi connection in daisy chain operation to save c interface pins. the number of devices connected in daisy chain is unlimited. figure 8. daisy chain topology 3.4 spi timing figure 9. spi timing single chain two devises in one daisy chain three devises in one daisy chain shift register c sck cs1 sck sck cs1 cs2 sck cs3 sck cs2 sck cs1 sck cs1 cs2 cs3 ic c ic b ic a cs1: low for 48 clocks sck cs2: low for 32 clocks sck cs3: low for 16 clocks sck reads from ic a--c reads from ic d-e reads from ic f writes from ic d-e writes from ic f writes into ic a--c ic d ic e ic f so si si so si so si do si so si so si so shift register shift register shift register shift register shift register shift register ac00659 t cnncs t hclch t sclcl t cll t clh t hclcl t sclch t csdv t pcld t scld t hcld t pchdz msb msb lsb lsb fsi so si sck cs ac00660
l9958 device description doc id 17269 rev 1 15/38 3.5 spi communication failure in case of "no sck edge" when cs = '0', th e transfer is considered as valid: no error is returned to the c. the answer of last command is sent during next transfer. when the number of sck period is different from 0 or multiple of 16, next spi answer is all zero. figure 10. spi zero clock communication 3.6 5 v and 3.3 v output compatibility in order to ensure a full compat ibility with 5v and 3.3v mcu pe ripherals, the pin vddio is dedicated to supply the output buffer of so . the overall current consumption on vddio is "ivddio". a parasitic current from the pin so could flow through the pin vddio in case of over-voltage on so pin vs. vddio pin. cs si fsi bit so ac00682 command n command n+1 answer to cmd n answer to cmd n-1
current regulation l9958 16/38 doc id 17269 rev 1 4 current regulation to protect the actuator and limit power dissipation, a two-level chopper current limitation is integrated as shown in figure below. the current is measured by sense cells integrated in the low-side switches. as soon the upper current limit ?ih? is reached, both low-side drivers are switched on to allow free-wheeling recircul ation, until the lower current limit ?il? is reached. during the current regulation, all the slew rate controls are disabled in order to minimize the power dissipation. four current limit levels can be set by the spi control bits 0 and 1. in order to achieve very precise current threshold and ripple, an external resistance is required (1 % accuracy on all temp range/lifetime) to generate a current reference. detailed values for current thresholds and ripple are reported in ta b l e 9 . figure 11. current limitation 4.1 temperature-depend ent current regulation in order to reduce power dissipation and thus the junction temperature, above a temperature twarn = 160 c, current regulation high limit linearly decreases with temperature, to reach about 2.5 a at tsd = 175 c (shutdown temperature). when this thermal threshold is reached during a current limitation phase, the information is stored and latched in a coding of bits called " twarn ". this bit can be reset only if the settings conditions (t j > twarn and i lim = 0) are not present anymore. this feature is mainly used to reduce the power dissipation and thus the junction temperature. table 9. current limitation programmability cl_2 cl_1 current limit (typical values) 0 0 2.5 a 0 1 4 a 1 0 6.6 a (default value) 1 1 8.6 a time limitation current tb: blanking time tb: blanking time current ih il ac00661
l9958 current regulation doc id 17269 rev 1 17/38 figure 12. temperature dependent current regulation 4.2 current regulation wi th low-inductive loads each time output stages are turned off, an internal timing starts for duration toff-min . whenever turn-on is reached in a time toff that is shorter than toff-min , output stages are kept off, until toff-min is reached. in such case the ripple control could be not so precise as specified. figure 13. current regulation with different loads 4.3 slew rate control in case of current limitation on low-side the slew rate control can be done on voltage and current or only on voltage. this can be selected by spi through the bit isr_dis. the slew rate of each high-side power transistor of the bridge is controlled either during turn-on and turn-off (current and voltage slew rate). the same setting is applied for both switching. moreover, this slew rate is configurable by spi in order to get the best trade-off between conducted/radiated emi and power dissipation during switching. the slew rate i 8.6 2.5 twarn tsd tj ac00662 tb current ih il tb time tb toff toff toff-min toff-min out1,2 high inductive load low inductive load
current regulation l9958 18/38 doc id 17269 rev 1 selection can be done "on the fly" by spi. the corresponding bits are called " vsr " and " isr ". no external component is needed to select the slew rate range. only the power transistors not used for freewheeling can be adjusted, the two others can be controlled with a preset slew rate. the couples of value de fined to fulfill most of the applic ation requirements are described in the table below. the required accuracy is 50 % for an output current from 1a to 8a and with output voltage up to 19 v. the overall delay implemented between high-side and low-side transistor switching must be adjusted automatically to avoid any cross-conduction through one half-bridge in all conditions. in case of current limitation and any detection that put the bridge in tri-state, the slew rate is not related anymore to the preset bits " vsr "; " isr " but to a dedicated faster slew rate control named "super fast" mode. the automatic change from spi selectable to super fast slew rate is described hereafter. figure 14. slew rate switching strategy table 10. slew rate control on low side mos range vsr isr dv/dt (v/s) di/dt (a/s) 1 ( default value )0 0 4 3 2014 0.3 3102 3 4112 0.3 no sr control not selectable 14 14 t off-min time is started at each hs switched-off while in sfrs mode (end of blanking or pwm falling edge) t off-min t b t b t off-min t off-min when (i < il) and (after t off-min ) and i_pwm = '0', l9958 go back to nsr (otherwise l9958 remains in sfsr mode) ih 0 i ls t nsr (*) nsr (*) sfsr (*) blanking pwm current_lim slew rate (*) nsr: normal slew rate note: current limitation state is reached when i > il the end of blanking (mos is switched-off by the device, user looses contr ol). this information is latched in ilim spi bit. when toff-min is started due to pwm falling edge in sfsr, the ilim spi bi t is not set (mos is switched-off by user). il once i < il, and after t off-min l9958 leaves current limitation once i > ih, we start blanking and in sfsr sfsr: super-fast slew rate pwm control remains active during blanking (user can switch-off). ac00664 ignored (t off_min )
l9958 diagnostics and protections doc id 17269 rev 1 19/38 5 diagnostics and protections a detailed diagnostic of the h-bridge is available through spi communication. the 16 bits diagnostic word is sent back to the mcu in return of a command word. the diagnostic word is used to report two kinds of information: h-bridge failures: ? over-current on each transistor in on-state, ? vps under-voltage, ? vdd over-voltage, ? over-temperature, ? open-load in on-state, ? off-state diagnostic. h-bridge functional status: ? current limitat ion condition, ? current limitation decreasing condition, ? disable / enable status. 5.1 diagnosis reset strategy 5.1.1 reset requests except "act" and "vs_uv" bits, all the others are latched and can only be released by: transition from "disable" to "enable" on di / en pins, diagnostic register read by spi (see details on each failure release) depending on bit "dr", power-on-reset condition. when the diagnostic register is reset, the bridge is switched back to normal mode driven by dir and pwm. all the settings are kept as before the failure. in case of spi read, no additional action on di / en is needed. 5.1.2 diagnosis reset bit in case of "dr" set to low (default value), all the bits of the diagnostic register can be reset by the three possibilities descr ibed in previous section. in case of "dr" set to high, the over-current, vdd over-voltage and over-temperature diagnostic bits can not be reset by spi read and therefore, the bridge is kept in tri-state until a transition from "disable" to "enable" on di/en pins or power-on-reset condition. table 11. diagnosis reset strategy dr diagnosis reset strategy 0 all diagnostic bits reset at each spi reading (default) 1 over current bits (8..11) + temp. shutdown tsd bit (6) + vdd over voltage bit (3) not reset by spi
diagnostics and protections l9958 20/38 doc id 17269 rev 1 5.2 protection and on state diagnostics l9958 is protected against short circuits, overload and invalid supply voltage by the following measures. 5.2.1 over-current on hi gh-side - short to ground the high-side switches are protected against a short of the output to ground by an over- current shutdown. if a high-side switch is turned on and the current rises above the short circuit detection current ioc all output transistors are turned off after a filter time toc_ls and the error bits "overcurrent on high side 1 (2)", oc_hs1 ( oc_hs2 ) are stored in the internal status register. 5.2.2 over-current on lo w-side - short to vs due to the chopper current regulation, the low-side switches are already protected against a short to the supply voltage. to be able to distinguish a short circuit from normal current limit operation, the current limitation is deactivated for the blanking time t b after the current has exceeded the current limit threshold ih. if the short circuit detection current i oc is reached within this blanking time, a short circuit is detected. all output transistors are turned off and the according error bit ?over-current on low side 1 (2)?, oc_ls1 ( oc_ls2 ) is set. 5.2.3 short circuit over-load if, during the blanking time ( t b ) of the current regulation mode, the current reaches the i oc threshold; after a filtering time, the output mos are switched off and the ?short circuit over load? can be checked by the reading of the overcurrent bits of the dia_reg (please refer to ta bl e 8 bit 8, 9,10 and 11). figure 15. diagnostics for scb / scol 5.2.4 open load in on state to perform the open load diagnosis in on state, the flag ol_on has to be set high through spi. after every open load diagnosis in on state, the ol_on flag is resetted, to perform a new open load diagnosis in on state the ol_on flag has to be set again. time tb:blanking time curre overcurrent fault detected tracking nt ih il ioc tb:blanking time on output stage off
l9958 diagnostics and protections doc id 17269 rev 1 21/38 this disable the turning on of the low-side drivers during current recirculation. the current flows through the body diode of the low-side mos for a fixed time. at the end of this fixed time the vout voltage is sampled and the possible open load condition detected (see figure 16 ). figure 16. open load in on state - low-side current recirculation 5.2.5 over-temperature when twarn is reached, thermal current reduction is activated, and the information is stored and latched. when tsd is reached, the ? tsd ? bit is set and all output transistors are put in tri-state conditions as long as a reset is applied. 5.2.6 vs under-voltage shutdown if the supply-voltage at the v s pins falls below the under-voltage detection threshold vs_uv_off , the outputs are set to tri-state and the error bit "undervoltage at v s " is set. a filtering time " tuv_vs " is implemented to avoid unwanted detection due to parasitic glitches. the information is transferred into the spi register in a bit called " vs_uv ". this bit is not latched. as soon as the voltage rises again above the vs under-voltage threshold (hysteresis implemented), the bridge is switched back to normal mode driven by dir and pwm. all the settings are kept as before the under-voltage event. pwm ol_on fault -0.7v gnd low side recirculation diangonsis off diangonsis on reset set reset ls mos on ls mos on tu c tu c ls mos off ls mos off voutx set open load detected! open load occurred! spi activity to write ol_on bit ac00666 table 12. over-temperature tsd comments bridge state fsi 1 tj > tsd tri-state- 1 0 (default) tj < tsd - 0
diagnostics and protections l9958 22/38 doc id 17269 rev 1 figure 17. battery voltage monitoring 5.2.7 vdd over-voltage detection although the vdd input pin and all i/o's are able to withstand up to 19 v, an over-voltage circuitry is implemented to ensure that the bridge is kept in tri-state when the vdd voltage is higher than the vdd overvoltage threshold " vdd_ov_off " for duration longer than " tov_vdd ". the information is detected and stored into the spi register in a bit called " vdd_ov ". the bridge is kept in tri-state as long as an appropriate reset is not requested (see section 5.1 ). 5.2.8 vdd under-voltage detection when the vdd voltage falls below the under-voltage detection threshold " vdd_uv_off " for duration longer than " tuv_vdd ", the bridge is switched to tri-state. in such a condition, the l9958 is going in sleep mode. when the voltage increases above the threshold (hysteresis implemented), the l9958 starts with all the settings reset to their default values (power on reset). 5.2.9 output s hort protection the l9958 can sustain short on the outputs. in case of short to gnd, short to battery or short between outputs the battery voltage cannot exceed 18 v. the connection of a 100 f decoupling capacitor as close as possible to v s pin and the gnd connection of the slug or of the exposed pad is mandatory to improve the robustness. table 13. vs under-voltage vs_uv comments bridge state fsi 1 vs < vs_uv_off hi z 1 (not latched) 0 (default) vs > vs_uv_on - 0 vs vs_uv vs_uv tuv_vs t vdd_ov_off hi-z 1 (latched) 0 (default) vdd < vdd_ov_on - 0
l9958 diagnostics and protections doc id 17269 rev 1 23/38 5.3 off-state diagnosis this diagnostic is performed in any off-state condition, just after ignition key-on or during an off-state phase occurring after an on-state phase of the bridge. 5.3.1 off-state detection scheme in order to avoid any wrong diagnostic, a filtering time " tdiag_off " is applied before performing the detection if the bridge was in on-state before. this filtering time is not applied in case of detection after key on. figure 18. off-state detection scheme 5.3.2 open load detection an equivalent resistor of 100 k (typ.) is targeted for open-load detection. in order to avoid any unwanted supply of the bridge through the high-side transistor body diode during off-state measurement, the current source is connected only if vs is higher than the vs under-voltage threshold. figure 19. open load detection the diagnostic is based on a closed loop voltage control on out1 and associated current measurement. a voltage amplifier forces a constant voltage on out1 through two current sources (high- side source and low-side current sink). the out2 is pulled-down through a constant current sink. based on the current flowing out of the amplifier (ip ? in) compared to several current thresholds, open-load as well as short-circuit to ground and battery can be detected. por di off off off off sleep on on on en diag spi t diag_off t diag_off diag done diag done diag done no diag no diag no diag no diag no diag no diag no diag no diag diag done no diag no diag no diag no diag no diag no diag ac0066 8 10 k 200 k 100 k load connected open load typical value for detection ac0066 9
diagnostics and protections l9958 24/38 doc id 17269 rev 1 figure 20. off-state diagnostic principle 5.4 h-bridge functional status three bits in the diagnosis register are used to give a feedback about the state of the h- bridge. status are current limitation (bit 4 "c_lim"), temperature warning (bit 5 "t_wrn") and bridge enable status (bit 7 "act"). those bits do not report a failure but only a functional state of the h-bridge that could be useful to change the control strategy mainly in term of power dissipation.
l9958 electrical specifications doc id 17269 rev 1 25/38 6 electrical specifications 6.1 absolute maximum ratings the component must withstand the overall following stimulus without any damage or latch- up. beyond these values, damage to the component may occur. note: in case of load dump condition, status of device outputs is kept unchanged. 6.2 thermal data table 15. absolute maximum ratings symbol parameter test condition min. max. unit v ps supply voltage continuous transient (0.5 s; i 10 a) -1 -2 40 40 v v dd logic supply voltage 0 v < v ps < 40 v -0.3 19 v v ddio sdo supply voltage 0 v < v ps < 40 v -0.3 19 v v i logic input voltage 0 v < v ps < 40 v 0 v < v dd < 19 v -0.3 19 v v o logic output voltage 0 v < v ps < 40 v 0 v < v dd < 18.7v -0.3 vddio+0.3 v output pins (outx, vps) esd compliance eia/jesd22-a114-b 4 - kv input pins 2 - - iso 7637 pulses cf. standards - - - - latch-up immunity jedec standard -100 +100 ma table 16. thermal data symbol parameter test condition min. max. unit t j junction temperature failure condition -40 otsd c lifetime -40 150 t stg storage temperature - -55 150 c t amb ambient temperature 0 v < v ps < 40 v -40 125 c r thj-case thermal resistance junction to case (1) package powerso-20 - 1 c/w package powerso16 - 1 package powersso24 - 2 1. guaranteed by design an d package characterization.
electrical specifications l9958 26/38 doc id 17269 rev 1 figure 21. thermal impedance (junction-ambient) of power packages 6.3 range of functionality within the range of functionality, all l9958 functionalities have to be guaranteed. all voltages refers to gnd. currents are positive into and negative out of the specified pin. 0 5 10 15 20 25 30 35 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (oc/w) pwsso24 on 2s2p pwsso24 on 2s2p th. enh. pwso20 on 2s2p pwso20 on 2s2p th. enh 0 5 10 15 20 25 30 35 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (oc/w) pwsso24 on 2s2p pwsso24 on 2s2p th. enh. pwso20 on 2s2p pwso20 on 2s2p th. enh ac00670 table 17. range of functionality pos. symbol parameter test condition min. typ. max. unit fr1 v ps supply voltage - vps_uv_off 14 28 (1) v fr2 dv ps /d t supply voltage slew rate - -20 - 20 v/s fr3 v dd logic supply voltage - vdd_uv_off 5 vdd_ov_off v fr4 v i logic input voltage (sdi, sclk, ncs, di, en, dir, pwm) see also table 15: absolute maximum ratings . -0.3 - vdd_ov_off v fr5 v ddio sdo output voltage - 3 - 5.5 v fr6 f spi spi clock frequency max apply freq. = 5 mhz 5 - tbd mhz 1. in load dump conditions v ps ranges between 28v and 40v. during load dump, status of device outputs is kept unchanged,
l9958 electrical specifications doc id 17269 rev 1 27/38 6.4 electrical characteristics t case = -40 c ... 125 c unless otherwise specified, v dd = 4.5 v ... 5.5 v unless otherwise specified v ps = 4 v ... 28 v unless otherwise specified all voltages refer to gnd. currents are positive into and negative out of the specified pin. 6.4.1 device supply 6.4.2 device supply monitoring table 18. device supply pos. symbol parameter test condition min. typ. max. unit 1.1 i ps power supply current v dd < 0.7 v; v ps = 16 v from -40 c to 25 c --20a v dd < 0.7 v; v ps = 16 v at 125 c --35a f pwm = 0, i out = 0 - - 20 ma 1.2 i out leakage current on output br idge in tri-state - - 100 a 1.3 i cc logic-supply current v dd >v dd_uv_on f pwm = 0 --5ma f pwm = 20 khz (average value) --5ma table 19. device supply monitoring pos. symbol parameter test condition min. typ. max. unit 2.1 v ps_uv_off v ps under-voltage threshold v ps decreasing - - 4 v 2.2 v ps_uv_on v ps under-voltage threshold v ps increasing - - 4.5 v 2.3 v ps_uv_hyst v ps under-voltage hysteresis - 0.1 - - v 2.4 t uv_vps v ps under-voltage filtering time v ps decreasing 1 - 3 s 2.5 v dd_uv_off v dd under-voltage threshold v dd decreasing 3 - 3.7 v 2.6 v dd_uv_on v dd under-voltage threshold v dd increasing 3.3 - 4 v 2.7 v dd_uv_hyst v dd under-voltage hysteresis - 0.1 - - v 2.8 t uv_vdd v dd under-voltage filtering time v dd decreasing 1 - 4 s 2.9 v dd_ov_off v dd over-voltage threshold v dd increasing 5.8 - 6.8 v 2.10 v dd-ov_on v dd over-voltage threshold v dd decreasing 5.5 - 6.5 v 2.11 v dd_ov_hyst v dd over-voltage hysteresis - 0.1 - - v 2.12 t ov_vdd v dd over-voltage filtering time v dd increasing 60 100 140 s
electrical specifications l9958 28/38 doc id 17269 rev 1 6.4.3 spi table 20. spi pos. symbol parameter test condition min. typ. max. unit 3.1 f spi clock frequency (50 % duty cycle) -5-- mhz 3.2 t sdo_trans sdo transition speed, 20-80 % v sdo = 5v, c load = 50 pf (1) 5-30 v sdo = 5 v, c load = 150 pf 5-50ns 3.3 t clh minimum time sclk = high - 75 - ns 3.4 t cll minimum time sclk = low - 75 - ns 3.5 t pcld propagation delay (sclk to data at 10% of sdo rising edge) ---40ns 3.6 t csdv ncs = low to data at sdo active ---85ns 3.7 t sclch sclk low before ncs low (setup time sclk to ncs change h/l) -75--ns 3.8 t hclcl sclk change l/h after ncs = low -75--ns 3.9 t scld sdi input setu p time (sclk change h/l after sdi data valid) -40--ns 3.10 t hcld sdi input hold time (sdi data hold after sclk change h/l) -40--ns 3.11 t sclcl sclk low before ncs high - 100 - - ns 3.12 t hclch sclk high after ncs high - 100 - - ns 3.13 t pchdz ncs l/h to sdo @ high impedance ---75ns 3.14 t onncs ncs min. high time - 300 - ns 3.15 - capacitance at sdi, sclk; ncs - - - 14 pf - capacitance at sdo - - - 19 pf 3.16 t fncs ncs filter time will be ignored) guaranteed by design (pulses = tfncs guaranteed by design 10 - 40 ns 3.17 v ddio supply voltage for sdo output buffer -3-5.5v 3.18 i vddio current consumption on vddio - - - 1 ma 3.19 sdo_h high output level on sdo i sdo = 1.5 ma v ddio - 0.4 --v 3.20 sdo_l low output level on sdo i sdo = 2 ma - - 0.4 v 3.21 i sdo tri state leakage current ncs = high v ddio = 5 v -5 - 5 a 1. not tested ? guaranteed by c load = 150 pf measurement
l9958 electrical specifications doc id 17269 rev 1 29/38 6.4.4 digital inputs: ttl // 3.3v / 5v cmos compatible 6.4.5 bridge output drivers table 21. digital inputs: ttl // 3.3v / 5v cmos compatible pos. symbol parameter test co ndition min. typ. max. unit 4.1 v ih input voltage high - 2 - vdd+0.3 v 4.2 v il input voltage low - -0.3 - 0.8 v 4.3 hysteresis of input voltage - 200 - - mv 4.4 i inl input current source for: di / ncs / sclk / sdi v in = 0 v -100 - -30 a v in = 5 v no back supply allowed -- 5 4.5 i inh input current sink for: en / dir / pwm v in = 5 v 30 - 100 a v in = 0 v -5 - - 4.6 v rext external resistor - - 1.24 - v r ext --10-k overall tolerance can be taken as 3.5 % -1 -% table 22. bridge output drivers pos. symbol parameter test condition min. typ. max. unit 5.1 r dson_h high-side transistor r dson t j = 150 c, i out = 3 a 4v < v ps < 5 v --300 m t j = 150 c, i out = 3 a v ps > 5 v --150 5.2 r dson_l low-side transistor r dson t j = 150 c, i out = 3 a 4v < v ps < 5 v --300 m t j = 150 c, i out = 3 a v ps > 5 v --150 5.3 v bd_h body diode forward voltage drop high-side transistor i diode = 3 a - 1.2 2 v 5.4 v bd_l body diode forward voltage drop low-side transistor i diode = 3 a - 1.2 2 v
electrical specifications l9958 30/38 doc id 17269 rev 1 6.4.6 over-temperature monitoring 6.4.7 current limitation an d over-current detection table 23. over-temperature monitoring pos. symbol parameter test condition min. typ. max. unit 6.1 otwarn over-temperature warning - 150 - 170 c 6.2 otsd over-temperature shut-down - 170 - 200 c 6.3 othyst over-temperature hysteresis - 10 - - c 6.4 t tsd over-temperature filtering time guaranteed by clock measurement -36-s table 24. current limitation and over-current detection pos. symbol parameter test condition min. typ. max. unit 7.1 i lim_h current limitation high threshold cl1:0 = 00; -40 c t j 150 c 2 2.5 3.1 a cl1:0 = 01; -40 c t j 150 c 3.5 4 4.85 cl1:0 = 10; -40 c t j < 25 c 5.5 6.75 8 cl1:0 = 10; 25 c t j 150 c 5.5 6.6 7.7 cl1:0 = 11; -40 c t j < 25 c 7.8 9.1 10.4 cl1:0 = 11; 25 c t j 150c 7.6 8.6 9.6 cl1:0 = xx, t j = otsd 2 2.5 3 7.2 i lim_l current limitation low threshold cl1:0 = 0x; -40 c t j 150 c i lim_h ?0.2 i lim_h - 0.5 i lim_h - 0.8 a cl1:0 = 10; -40c t j < 25 c ilim_h? 0.35 ilim_h- 0.65 ilim_h- 0.95 cl1:0 = 10; 25 c t j 150c ilim_h? 0.35 ilim_h- 0.55 ilim_h- 0.8 cl1:0 = 11; -40c t j < 25c ilim_h? 0.4 ilim_h- 0.7 ilim_h- 1 cl1:0 = 11; 25 c t j 150c ilim_h? 0.4 ilim_h- 0.55 ilim_h- 0.85 7.3 t limh high current limitation threshold filtering time can be included in t blanck 0.1 - 1 s 7.4 t liml low current limitation threshold filtering time -1-3s 7.5 t offmin current limitation delay time - 30 - 45 s 7.6 t b blanking time - 4.9 - 8.7 s
l9958 electrical specifications doc id 17269 rev 1 31/38 6.4.8 diagnostic of open-load in on-state 6.4.9 off-state diagnostic 7.7 ioc_ls ioc-hs low-side over-current threshold high-side over-current threshold cl1:0 = 0x; -40 c t j 150 c 5.5 7.7 9.9 a cl1:0 = 1x; -40c t j < 25 c 9.3 12 15 cl1:0 = 1x; 25 c t j 150c 9.3 11.5 14 tr a ck i n g cl1:0 = 0x; cl1:0 = 10; -40 c t j 150 c i lim_h +2 - - cl1:0 = 11; -40 c t j 150 c i lim_h +1.3 - - 7.8 to c _ l s to c _ h s low-side & high-side over-current detection filtering time -1-2s table 24. current limitation and over-current detection (continued) pos. symbol parameter test condition min. typ. max. unit table 25. diagnostic of open-load in on-state pos. symbol parameter test condition min. typ. max. unit 8.1 is_ol-on current source t j = -40 c (go-no-go functional test) 50 - 120 a t j = 25 c to 150 c (go-no-go functional test) 50 - 100 8.2 tmeas_on detection time (settling time) - - 3 5 s table 26. off-state diagnostic pos. symbol parameter test condition min. typ. max. unit 9.1 r ol load detection threshold 10 60 200 k 9.2 tdiag_off delay time before enabling off- state diagnostic structure diag after on-state guaranteed through scan 100 125 150 ms 9.3 t diag-off_1 off-state diag filtering time when out 1 and/or 2 decrease from v ps used each time out pins are released from vps (after release of scb, after tdiag_off) guaranteed through scan 2.4 3 3.6 ms 9.4 t diag_off_2 off-state diagnostic filtering time on failure detection one symmetric filter for each failure type (ol, scg, scb) guaranteed through scan 200 250 300 s 9.5 t clock oscillator frequency - 4 - 6 mhz
electrical specifications l9958 32/38 doc id 17269 rev 1 6.4.10 timing characteristics table 27. timing characteristics pos. symbol parameter test condition min. typ. max. unit 10.1 f pwm pwm frequency - - - 20 khz 10.2 t don delay time for switch-on r load @ i out = 3 a pwm 90% v out (or 10 % i out ) --10s t doff delay time for switch-off r load @ i out = 3 a pwm 10 % v out (or 90% iout) --10s t d delay time: symmetry pwm accuracy = 1% @ 2khz --5s 10.3 t d_dis disable delay time di / en 90% outx @ i out = 3 a --6s 10.4 t d_en enable delay time di / en 10 % out - - 6 s 10.5 t d_pow power-on delay time dir= pwm=en=1 / di=0 no load / v ps = v dd increasing v ps = v dd 10 % v out1 (= v ps ) --200s 10.6 t d_filter di / en digital filter time - 1 - 3 s 10.7 t rise_h low-side transistor rise time non selectable by spi 0.04 - 0.2 s 10.8 t fall_h low-side transistor fall time non selectable by spi 1 - 2.2 s 10.9 dv out/ d t voltage slew rate for high-side transistors (measurement is performed between 30 % and 70 % of the slope) super fast mode 8 14 24 v/s vsr = 0 2 4 6 vsr = 1 1 2 3 10.10 di out /d t current slew rate for high-side transistors (measurement is performed between 40 % and 60 % of the slope) super fast mode (no current sr ctrl // dependant on voltage sr ctrl) 71424 a/s isr=0 1.5 3 4.5 isr=1 0.15 0.3 0.45 10.11 t diag timing for reliable diagnostic guaranteed through scan pattern 35 - 55 s
l9958 application circuit doc id 17269 rev 1 33/38 7 application circuit figure 22. application circuit out1 out2 vs cp battery l9958 100f 39v 5v 5v/3.3v dc gnds vdd so si sck ncs dir pwm en di rext c power supply vddio out1 vs cp battery 1f gnds vdd so si sck ncs dir pwm en di rext vddio 100nf 100nf 10f 10nf 100nf 22k 10k 22k 10nf ac00671
package information l9958 34/38 doc id 17269 rev 1 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 23. powerso-20 mechanical data and package dimensions outline and mechanical data e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45? detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a3.60.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 (2 ) 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h1.10.043 l 0.8 1.1 0.031 0.043 n 8?(typ.) s 8?(max. ) t 10 0.394 (1) ?d and e1? do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006?) - critical dimensions: ?e?, ?g? and ?a3?. (2) for subcontractors, the limit is the one quoted in jedec mo-166 powerso-20 0056635 i jedec mo-166 weight: 1.9gr
l9958 package information doc id 17269 rev 1 35/38 figure 24. powerso16 mechanical data and package dimensions dim. mm inch min. typ. max. min. typ. max. a1 0 0.05 0.1 0 0.002 0.004 a2 3.4 3.5 3.6 0.133 0.137 0.141 a3 1.2 1.3 1.4 0.048 0.05 0.052 a4 0.15 0.2 0.25 0.006 0.007 0.01 a 0.2 0.007 b 0.27 0.35 0.43 0.011 0.013 0.017 c 0.23 0.27 0.32 0.009 0.01 0.012 d 9.4 9.5 9.6 0.37 0.374 0.377 d1 7.4 7.5 7.6 0.291 0.295 0.299 d 0.1 0.004 e (1) 13.85 14.1 14.35 0.545 0.555 0.565 e1 9.3 9.4 9.5 0.366 0.37 0.374 e2 7.3 7.4 7.5 0.287 0.291 0.295 e3 5.9 6.1 6.3 0.232 0.24 0.248 e 0.8 0.031 e1 5.6 0.22 f 0.5 0.019 g 1.2 0.047 l 0.8 0.95 1.1 0.031 0.037 0.043 r1 0.25 0.01 r2 0.8 0.031 t 2? (min.), 5? (typ.), 8? (max.) t1 6? (typ.) t2 10? (typ.) (1) resin protrusions not included (max value: 0.1mm per side). powerso16 a3 a2 d1 e3 0.35 f u seating plane 9 16 8 1 e b e2 d set detail k pso16mec g m d l l m m a c e1 r1 r1 t2 t1 see detail j r2 e r1 t1 t2 e1 a1 a4 c c leads coplanarity detail j set detail k t gauge plane l outline and mechanical data
package information l9958 36/38 doc id 17269 rev 1 figure 25. powersso24 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.45 0.0965 a2 2.15 2.35 0.084 0.0925 a1 0 0.10 0 0.003 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.012 d (1) 10.10 10.50 0.398 0.413 e (1) 7.40 7.60 0.291 0.299 e0.80 0.031 e3 8.80 0.346 f2.30 0.090 g 0.10 0.004 g1 0.06 0.002 h 10.10 10.50 0.398 0.413 h 0.40 0.016 k 0? (min.), 8? (max.) l 0.55 0.85 0.0217 0.0335 o 1.20 0.047 q 0.80 0.031 s 2.90 0.114 t 3.65 0.143 u 1.0 0.039 n 10? (max) x 4.10 4.70 0.161 0.185 y 6.50 4.90 (4) 7.10 5.50 (4) 0.256 0.192 (4) 0.279 0.216 (4) (1) ?d and e1? do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15mm (0.006?) (2) no intrusion allowed inwards the leads. (3) flash or bleeds on exposed die pad shall not exceed 0.4 mm per side (4) variation for small window leadframe option. powersso24 7412818 i (exposed pad down)
l9958 revision history doc id 17269 rev 1 37/38 9 revision history table 28. document revision history date revision changes 16-mar-2010 1 initial release.
l9958 38/38 doc id 17269 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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